1. Field of the Invention
The present invention relates to solid-state image sensing devices, methods and circuits for operating solid state image sensing devices and an imaging system using the same.
2. Description of Related Art
Integrated circuit image sensors are finding applications in a wide variety of fields, including medical imaging, machine vision, robotics, guidance and navigation, automotive applications, and consumer products such as digital camera and video recorders. Imaging circuits typically include a two dimensional array of photo sensors. Each photo sensor includes one picture element (pixel) of the image. Light energy emitted or reflected from an object impinges upon the array of photo sensors. The light energy is converted by the photo sensors to an electrical signal. Imaging circuitry scans the individual photo sensors to readout the electrical signals. The electrical signals of the image are processed by external circuitry for subsequent display.
Modern metal oxide semiconductor (MOS) design and processing techniques have been developed that provide for the capture of light as charge and the transporting of that charge within active pixel sensors and other structures so as to be accomplished with almost perfect efficiency and accuracy.
One class of solid-state image sensors includes an array of active pixel sensors (APS). An APS is a light sensing device with sensing circuitry inside each pixel. Each active pixel sensor includes a sensing element formed in a semiconductor substrate and capable of converting photons of light into electronic signals. As the photons of light strike the surface of a photoactive region of the solid-state image sensors, free charge carriers are generated and collected. Once collected the charge carriers, often referred to as charge packets or photoelectrons are transferred to output circuitry for processing.
An active pixel sensor also includes one or more active transistors within the pixel itself. The active transistors amplify and buffer the signals generated by the light sensing element to convert the photoelectron to an electronic signal prior to transferring the signal to a common conductor that conducts the signals to an output node.
Active pixel sensor devices are fabricated using processes that are consistent with complementary metal oxide semiconductor (CMOS) processes. Using standard CMOS processes allows many signal processing functions and operation controls to be integrated with an array of active pixel sensors on a single integrated circuit chip.
Refer now to FIG. 1 for a more detailed discussion of an active pixel image sensor array 5 of the prior art. The photodiode 15 are formed within the surface a substrate. A floating diffusion 25 is formed within the substrate to function as capacitive storage nodes for hold charge accumulated within the photodiode's 15 depletion region. The transfer gate switches 20 are connected between the photodiode 15 and the floating diffusion 25 and is activated by the transfer gate signal 30 connected to the gate of the transfer gate switch 20. The source of the reset transistor 35 is connected to the floating diffusion 25 and the drain of the reset transistor 35 is connected to the power supply voltage source VDD. The reset signal 50 is connected to the reset transistor 35 to activate the reset transistor 35 to connect the floating diffusion 25 to the power supply voltage source VDD to reset the floating diffusion to the voltage level of the power supply voltage source VDD. During the activation of the reset transistor 35, the transfer gate switch 20 is activated to also reset the voltage level of the photodiode 15 to the voltage level of the power supply voltage source VDD and remove any residual photoelectrons from the depletion region of the photodiode 15.
The floating diffusion 25 is connected to the gate of the source follower transistor 40. The drain of the source follower transistor 40 is connected to the power supply voltage source VDD and the emitter of the source follower transistor 40 is connected to the drain of the row select switch transistor 45. The gate of the row select switch transistor 45 is connected to the row select signal 55. The source follower transistor 40 acts to buffer the electrical signal created by the photoelectron charge collected in the floating diffusion 25.
The photons 17 that impinge upon the photodiode 15 are converted to photoelectrons and collected within the photodiode 15. At the completion of an integration of the collection of the photoelectrons, the transfer gate signal 30 is activated to turn on the transfer gate switch 20 to transfer the collected photoelectrons to the storage node of the floating diffusion 25. When the collected photoelectrons are retained at the floating diffusion 25 the row select signal 55 is activated to turn on the row select switch transistor 45 to gate the pixel conversion output electrical signal PIX_OUT to row bus 60. The amplitude of pixel conversion output electrical signal PIX_OUT is indicative of the intensity of the light energy hv or the number of photons 17 absorbed by the photodiode 15. Once the pixel output electrical signal PIX_OUT is read out the reset signal 50 is activated to turn on the reset transistor 35 and the photodiode 15 and the floating diffusion 25 are emptied of the photoelectrons.
The pixel image sensors 10a, . . . , 10b, . . . , 10m, . . . , 10n are placed in columns and rows to form the array 5. Each of the pixel image sensors 10a, . . . , 10b, . . . , 10m, . . . , 10n are structured as described above. The gate of the row select switch transistor 45a, . . . , 45b, . . . , 45m, . . . , 45n of each pixel image sensor 10a, . . . , 10b, . . . , 10m, . . . , 10n on each row of the array 5 is connected to the row select signal 55a, . . . , 55n generated by the row control circuit 65. The source of each row select switch transistor 45a, . . . , 45b, . . . , 45m, . . . , 45n of each pixel image sensor 10a, . . . , 10b, . . . , 10m, . . . , 10n on each column of the array 5 is connected to a column sample and hold circuit 75a, . . . , 75n through the row buses 60a, . . . , 60n. 
The drain of each of the reset transistors 35 of the each pixel image sensor 10a, . . . , 10b, . . . , 10m, . . . , 10n of the array 5 is connected to a power supply voltage source VDD through a distribution network to each pixel image sensor 10a, . . . , 10b, . . . , 10m, . . . , 10n. The gate of the reset transistor 35 of each pixel image sensor 10a, . . . , 10b, . . . , 10m, . . . , 10n on each row of the array 5 is connected to the reset signal 50a, . . . , 50n generated by the row control circuit 65 for selectively resetting the floating diffusion 25 and the photodiode 15 of each pixel image sensor 10a, . . . , 10b, . . . , 10m, . . . , 10n. The gate of each transfer gate switch 20 of each pixel image sensor 10a, . . . , 10b, . . . , 10m, . . . , 10n on each row of the array 5 is connected to the transfer gate signal 30a, . . . , 30n generated by the row control circuit 65 for transferring the photoelectrons from photodiode 15 to the floating diffusion 25 of each pixel image sensor 10a, . . . , 10b, . . . , 10m, . . . , 10n. 
The floating diffusion 25 acts as the photoelectron storage node for each pixel image sensor 10a, . . . , 10b, . . . , 10m, . . . , 10n and is connected to the gate of the source follower source follower transistor 40. The drain of the source follower transistor 40 is connected to the power supply voltage source VDD and the source is connected to the drain of the row select switch transistor 45. The gate of the row select switch transistor 45 is connected to the row select signal 55 and the source is connected to the row bus 60a, . . . , 60n for connection to the column sample and hold/image readout circuit 70.
The row select signal 55 activates the row select switch transistor 45 to transfer the voltage at the source of the source follower transistor 40 to the row bus 60a, . . . , 60n for connection to the column sample and hold/image readout circuit 70. The voltage at the source of the source follower transistor 40 is proportional to the number of photons 17 that impinge upon each photodiode 15 of each pixel image sensor 10a, . . . , 10b, . . . , 10m, . . . , 10n. 
The column sample and hold circuit 75a, . . . , 75n combines the column pixel row operation (pixel reset, row select) and the column operation (the photo generation, photo sensing). The sample and hold signal SH 84 and the clamp signal 83 are activated and deactivated by the column sample and hold/image readout circuit to respectively activate the switches SW1 77 and SW2 80 to capture the pixel output electrical signal PIX_OUT indicative of the level of the intensity of the light energy 17 present on each of the photodiode 15 of each pixel image sensor 10a, . . . , 10b, . . . , 10m, . . . , 10n. This combination causes the output voltage of the column sample and hold circuit 75a, . . . , 75n to be equal to the differential voltage of pixel reset level and photo conversion electrical signal level, i.e., Vout=Vrst−Vsig. During the pixel readout, switch SW3 81 controlled by column select signal COL_SEL 82 transfers the differential voltage through the column bus COL_BUS 85 to the video amplifier 92 of the image readout circuit 90 that applies the gain factor and offset correction factor to the output signal. The output of video amplifier 92 is the analog output that is digitized by an analog-to-digital converter 94. The output of the analog-to-digital converter 94 is the digital data word 95 that is transferred to an image processor.
“Self-Scanned Image Sensors Based on Charge Transfer by the Bucket-Brigade Method”, Weimer, et al., IEEE Transactions on Electron Devices, November 1971, Vol.: 18, Issue: 11, pp.: 996-1003 describes solid-state image sensors which are internally scanned by charge transfer offer an alternative to sensors based on x-y addressing. Shift registers are employed for the x-y addressing.
“Transversal-Readout Architecture for CMOS Active Pixel Image Sensors”, Miyatake, et al., IEEE Transactions on Electron Devices, Vol. 50, no. 1, pp: 121-129, January 2003 provides a novel architecture for CMOS active pixel image sensors (APS's), which eliminates the vertically striped fixed pattern noise (FPN). An array of transversal-readout APS is shown with two vertical (row) shift registers for addressing the rows of the array and a horizontal shift register for addressing the columns of the array. One of the with two vertical (row) shift registers is for selecting a row for reset and the other is of the with two vertical (row) shift registers is for selecting the row for readout.
U.S. Pat. No. 6,037,979 (Yonemoto) teaches a solid-state imaging device with a vertical shift register for addressing the row of the imaging device and a horizontal shift register that selects gating switches to transfer the conversion signal from each pixel of a selected row to a single amplifier.
U.S. Pat. No. 6,184,928 (Kannegundla, et al.) provides split shift register addressing for array applications such as imaging arrays. A fast shift register is coupled to a slow shift register by a combinatorial circuit having inputs from the fast shift register and the slow shift register to providing the selected address.
U.S. Pat. No. 6,570,615 (Decker, et al.) teaches a pixel readout scheme for image sensors that has a single differential to single-ended amplifier. The signals from each pixel are correlated double sampled passed through the select switches to the single differential to single-ended amplifier to an analog multiplexer, and thence to a programmed gain amplifier to an analog-to-digital converter.
U.S. Pat. No. 6,903,768 (Ohsawa, et al.) describes a solid state image sensor device with unit cells of the image sensing cell array having horizontal rows and vertical columns that are read by turning on an address register by means of the vertical shift register. Those of the vertical signal lines in the optical black pixel region are connected with each other through a wiring. Since the vertical signal lines in the optical black pixel region are connected with each other by a wiring, even if outputs from an optical black pixel region vary in the pixels, the outputs are made averaged and uniform and a variation in fixed pattern noises between the horizontal lines are reduced.
U.S. Pat. No. 6,961,088 (Kameshima, et al.) teaches a sensor array having a sample and hold circuit connected to an analog multiplexer. The signal from a selected column of sensors is applied through the multiplexer to an analog-to-digital converter. A shift register provides a selection of the column for each of the sensors on a selected row.
U.S. Patent Application 2001/0033337 (Sakuragi) provides an image pickup apparatus that includes a two-dimensional image pickup area, a vertical line selector for selecting a reading row in the image pickup area, vertical signal lines arranged in columnar direction, for reading a detection signal emitted by a photodiode located in a selected row, and a horizontal selection transistor for continuously reading detection signals carried by the vertical signal lines and writing the signals to a horizontal signal line arranged like a row in a matrix. The horizontal signals are generated by a vertical shift register for selecting the row of the matrix. The signals from each photodiode are applied to a vertical signal line that are applied to a single amplifier. Each column has a sample and hold circuit and a select switch to apply the signals from the sample and hold circuit to the amplifier. A horizontal shift register select which of the switches and thus the columns that are to be selected.
U.S. Patent Application 2002/0001037 (Miyawaki, et al.) describes a photoelectric conversion device that has sensors arranged in columns and rows. The columns and rows are addressed by a horizontal and vertical shift register. The sense signals are selectively applied to a single amplifier to create an output signal.
U.S. Patent Application 2002/0044211 (Tujii, et al.) teaches an image sensing device with a vertical shift register for the addressing of rows of the array of the image sensing device. An analog multiplexer receives signals from the columns of the image sensing device and applies them to an analog-to-digital converter.
U.S. Patent Application 2005/0012836 (Guidash) provides an image sensor that includes pixel output analog multiplexers that enables sample and hold of the signals from either of the two columns of pixels into either of the associated column circuits.
U.S. Patent Application 2005/0168606 (Yonemoto) illustrates a solid-state imaging device with a shift register used for a horizontal (row) scanning device and a charge holding device at the bottom of each row with switches to connect to a serial output amplifier.
U.S. Patent Application 2004/0080650 (Hwang, et al.) describes a CMOS image sensor single chip integrated with an RF transmitter.